The present invention generally relates to semiconductor wafer manufacture in the presence of particle contamination, and more particularly to the field of yield forecasting in a real-time semiconductor wafer manufacturing environment.
Fabrication of semiconductor integrated circuits (ICs) is an extremely complex process that involves several hundred or more operations. They are fabricated by selectively implanting impurities into and applying conductive and insulative layers onto a semiconductor substrate. Semiconductor ICs (chips) are not manufactured individually but rather as an assembly of a hundred or more chips on a xe2x80x9cwafer,xe2x80x9d which is then diced up to produce the individual chips.
Increasing production yield is an ongoing problem in the manufacture of semiconductor chips. Because of various defects that can occur in the fabrication of a wafer, a significant number of wafer die have to be discarded for one reason or another, thereby decreasing the percentage yield per wafer and driving up the cost of the individual chips. Defects are typically caused by foreign particles, minute scratches, and other imperfections introduced during photoresist, photomask, and diffusing operations. Yield impacts the number of wafer starts at the inception of production needed to meet specific customer order quantities for finished chips at the end of the production line. With the high demand for semiconductor chips and more orders than can possibly be filled by a production facility, predicting yield to accurately gauge wafer starts and utilizing defect information to remove yield-detracting operations are important aspects of improving the efficiency and hence the output of the fabrication facility.
Wafer-scanning tools are utilized to identify defects that occur in the chip manufacturing process for the aforementioned purposes. Typically, such tools are located at a variety of positions along the production line and include automated-vision inspection stations for identifying visual irregularities in the wafer die as they move through the line. The irregularities, i.e., defects, are recorded according to their coordinates, estimate of size, or other parameters and are stored as records in a database. The records represent raw information that is then analyzed or otherwise processed offline to determine the impact, if any, of the identified defects on product yield. Some defects, for example, may not adversely affect yield as much as others, and correspondingly must be classified differently for analysis purposes.
Commercially available wafer scanning tools include those made by KLA Instruments Corporation of Santa Clara, Calif.; Tencor Instruments Corporation of Mountain View, Calif.; Inspex, Inc. of Billerica, Mass.; and numerous other manufacturers. Despite significant advances made in wafer-scanning technology, the various tools that are available suffer striking deficiencies. In particular, such tools lack the capability to perform certain advanced classification and analysis of defect information necessary to accurately determine the true impact of wafer defects on yield. While conventional tools offer simple data presentation capabilities, such as the display of wafer maps, histograms and charts, they do not adequately classify or process the defect data.
More specifically, a disadvantage suffered by scanning tools is that they do not adequately perform yield prediction operations beneficial in a manufacturing defect analysis, thereby limiting the utility. It is often desirable to further refine the defect data before manual inspection and classification of individual defects on the review station. Since each wafer can include so many defects, it would not be practical to manually review and classify each of them. It would be desirable to utilize a method to randomly choose a statistically meaningful sample, i.e., subset, of such defects for consideration.
Historically, the review station operator randomly picks sets of defects that seem interesting and then reviews and classifies them. However, it is difficult for humans to systematically choose defects for this purpose that will be representative of all of the defects on the wafer. Some review stations are equipped with the ability to randomly move to different defects which the operator can then review and classify. A problem though with conventional randomizing methods performed on review stations is that they are not necessarily accurate in representing a true sampling of the wafer. For example, picking defects at random tends to result in the inordinate picking of defects that are part of a big cluster, because there are more of them, while defects of other types and in other locations on the wafer are overlooked. Therefore, it would be desirable to adopt an automated and consistent method for randomly identifying for review defects of interest. This method could focus on defect subpopulations defined in terms of defect size ranges or, alternatively, in terms of locations on the wafer, so that the sample of defects chosen best reflects the conditions actually occurring on the wafer.
FIGS. 1 and 2 illustrate a semiconductor wafer 2, which includes five particles 4, and the semiconductor wafer 2xe2x80x2 contains eleven particles 4xe2x80x2.
FIG. 3 illustrates a schematic illustration of a semiconductor device in a semiconductor wafer. Circuit conductor lines 6 and 8 are designed in the semiconductor wafer to conduct electrical signals independently of one another. Due to imperfections in the semiconductor wafer manufacturing process, particle 10 has been introduced between conductors 6 and 8. Particle 10 does not interfere with either of conductors 6 and 8 and will generally not affect the functionality (or yield) of the semiconductor device or wafer. Accordingly, even though particle 10 is a result in a defect in the semiconductor wafer manufacturing process, the particle does not cause failure in the semiconductor device by disturbing signals flowing in conductors 6 and 8.
FIG. 4 is also a schematic illustration of a portion of a semiconductor device similar to the illustration of FIG. 3. However, in FIG. 4, particle 10xe2x80x2 is much larger than particle 10 of FIG. 3. In this example, particle 10xe2x80x2 is in contact with both conductors 6 and 8 at regions 12 and 14, respectively. If particle 10xe2x80x2 is able to conduct electricity, the independent operation of conductors 6 and 8 will be jeopardized, creating cross-talk between conductors 6 and 8. If different devices are connected to conductors 6 and 8, a single particle 10xe2x80x2 may destroy the two devices embedded in the semiconductor wafer. Accordingly, particle 10xe2x80x2 is what is commonly known as a xe2x80x9ckiller defectxe2x80x9d since particle 10xe2x80x2 may kill or prevent the normal operation of the semiconductor device which utilizes conductors 6 and 8. While the presence or absence of killer defects may be determined, it is important to utilize the defect characteristics in a semiconductor wafer.
FIGS. 5 and 6 are schematic illustrations of a portion of a semiconductor device for providing some additional background information regarding semiconductor defects. In FIG. 5, semiconductor device conductor lines 16 and 18 are separated by the distance 20. During the manufacturing process, particle 22 is introduced in the semiconductor wafer due to manufacturing defects or imperfections. Particle 22 has a diameter 24 and center point 26 as illustrated. In the situation illustrated in FIG. 5, particle 22 is in contact only with conductor 16 and is unable to be extended to contact both conductors 16 and 18. Therefore, particle 22 is considered to be a non-killer defect. Note that in this situation, the position of center 26 of particle 22, identified by dashed line 30, is spaced apart from the center position 28 of conductors 16 and 18 by distance 32. As particle 22 moves closer toward conductor 18, the center 26 of particle 22 will also move closer to center 28 or conductors 16 and 18 as illustrated in FIG. 6.
As shown in FIG. 6, the center 26 of particle 22 has moved closer to the center 28 of conductors 16 and 20. This is illustrated by the distance between center 28 and center line 30xe2x80x2 being 32xe2x80x2 which is smaller than the distance 32 in FIG. 5. Particle 22 is in contact with both conductors 16 and 20 and, correspondingly, is considered a killer defect. Thus, as the center 26 of particle 22 is moved closer to center 28 of conductors 16 and 20, the particle 22 will become more likely a killer defect. This, of course, presumes that particle 22 is large enough to be in simultaneous contact with both conductors 16 and 20.
A method for integrated yield management of semiconductor wafers being inspected for defects in a factory is disclosed. The present invention includes the steps of defining and using a critical area analysis to predict yield impact of pattern disturbing defects; defining and using spacial analysis to calculate the ratio of yield loss due to randomly distributed yield loss and regionally bound yield loss; defining and using yield loss mode analysis to quantify the extent of yield loss being attributed to modes related to each type of spacial yield loss; defining and using a yield loss manufacturing location to quantify yield loss during the manufacturing process for each yield loss mode; defining and using yield loss cause analysis to quantify yield loss at each node for each mode of yield loss due to variations in nodes of in-line monitors; and defining and using yield loss cause analysis to quantify yield loss at each node for each mode of yield loss due to node situational circumstances.